1. Field of the Invention
The invention generally relates to memory devices and, more particularly, to memory devices having memory cells arranged in a twin-cell array structure.
2. Description of the Related Art
The evolution of sub-micron CMOS technology has resulted in an increasing demand for high-speed semiconductor memory devices, such as dynamic random access memory (DRAM) devices, pseudo static random access memory (PSRAM) devices, and the like. Herein, such memory devices are collectively referred to as DRAM devices. Such devices utilize memory cells consisting of one transistor and one capacitor. Due to leakage, the memory cells require periodic refreshing to protect data that is stored in the memory cell from corruption or decaying over time. The data stored in the memory cell is automatically restored to a full logic level when accessed (e.g., via a read or write operation), but must be periodically refreshed when not accessed. Therefore, DRAM devices typically include refresh circuitry to facilitate memory cell refresh.
Because each row of cells must be accessed within a specified cell retention time, refresh operations occur frequently. As a result, refreshing memory cells is a power-consuming routine. In battery-powered computer systems (e.g., palm-top computers, cellular telephones, and other portable electronic devices), minimization of power consumption is critically important. In general, as the cell data retention time increases, the self refresh current decreases.
One approach that may reduce the power consumption of memory by increasing cell retention time is to arrange memory cells in what is known in the art as a twin-cell array structure. Twin-cell array structures, as the name implies, utilize two memory cells to store a single bit of information which inherently increases data retention time as more charge is used to store each bit. Complementary logic levels are stored in the two cells which, when accessed, are connected to differential inputs of a sense amplifier. By utilizing the same type of memory cells in twin-cell structures as in single-cell structures, data retention time can be increased without significant manufacturing process changes.
FIG. 1 shows a conventional twin-cell array structure 100, utilizing what is referred to as an open bit cell arrangement with sense amplifiers 104 arranged between arrays 110 of memory cells 107. In the illustrated scheme, two word lines, 102U and 102L, are activated simultaneously. This activation couples two adjacent memory cells 107U and 107L to one of differential inputs of the sense amplifier 104 via bit lines 103 and a single bit of data is written to or read from the two cells. Because DRAM cells store data as charge at each cell capacitor, if the stored charge for a single data bit is doubled, the data retention time can be easily extended without any process changes.
Unfortunately, this open bit line twin-cell structure has several problems. One problem arises because this structure requires dummy cell arrays 120A and 120B to provide reference signals for edge bit line sense amplifier arrays 130A and 130B. These dummy cell arrays include unused memory cells 124 that usually can not be used for storing data, so these cells result in chip size penalty. Another problem is that the simultaneous activation of two word lines, with a boosted word line voltage level, results in much more power consumption than conventional single word line activations. Still another problem is that capacitive loading difference between a bit line 103 (e.g., in an upper array) and a complementary bit line 103 (e.g., in a lower array) may be significant. When accessing two cells, they are connected only to a bit line. The capacitance loading difference may result in a larger offset voltage at the bit line sense amplifier, thus reducing the sensing margin.
Accordingly, there is a need for an improved sensing technique and twin-cell array structure.